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TDA7550/R TDA7551 TDA7552 TDA7553
DIGITAL SIGNAL PROCESSING IC FOR SPEECH AND AUDIO APPLICATIONS
PRODUCT PREVIEW
24-BIT, FIXED POINT, 50 MIPS DSP CORE LARGE ON-BOARD PROGRAM ROM AND DATA RAM (UP TO 16Kw ROM/RAM AND 16Kw RAM) INTEGRATED STEREO A/D AND D/A, 16-BIT SIGMA-DELTA PROGRAMMABLE CODEC SAMPLE RATE FROM 4 TO 48 kHz ON-BOARD PLL FOR CORE CLOCK AND CONVERTERS MANAGEMENT OF EXTERNAL FLASH/SRAM/DRAM MEMORY BANK I2C OR SPI SERIAL INTERFACE FOR EXTERNAL CONTROL 80-PIN TQFP, 0.65 mm PITCH AUTOMOTIVE GRADE (FROM -40 C to +85C) DESCRIPTION The TDA755X family is a high performances, fully programmable 24-bit, 50 MIPS Digital Signal BLOCK DIAGRAM
MULTIPLEXED BUS
TQFP80
Processor (DSP), designed to support several speech and audio applications, as Automatic Speech Recognition, Speech Synthesis, Speaker Verification, Echo and Noise Cancellation. Software for these applications is licenced by Lernout & Hauspie and NCTI. It offers an effective solution for this kind of applications because of the A/D and D/A converters and the big amount of memory integrated on chip.
I2C/SPI PORT
FLASH INTERFACE
SAI
ROM/RAM
RAM
8
FLAGS
DSP CORE
DAC
L ANALOG OUT R L ANALOG IN R
ADC PLL
D99AU1020A
September 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
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APPLICATIONS Real time digital speech and audio processing: speech recognition, speech synthesis, speech compression, echo cancelling, noise cancelling, speaker verification.
ABSOLUTE MAXIMUM RATINGS
Symbol VDDP VD, VIN Top Tstg Ptot Pads DC Supply Voltage Digital or Analog Input Voltage Operating Temperature Range Storage Temperature Range Total Maximum Power Dissipation Parameter Value -0.3 to VDD +0.3 -0.3 to VDDP +0.3 -40 to +85 -55 to +150 Unit V V C C mW
PIN CONNECTION
EMI_AD4
EMI_AD3
EMI_AD2
EMI_AD1
EMI_AD0
CLKOUT
REFCAP
CVDDA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 EMI_AD5 EMI_AD6 VDD GND EMI_AD7 EMI_A8 EMI_A7 EMI_A10 EMI_A11 EMI_A12 EMI_A13 EMI_A14 EMI_A15 VDD GND EMI_A16 EMI_A17 EMI_A18 EMI_A19 EMI_A20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND TEST3 SCK LRCK GND GPIO1 MOSI VDD SDI VDD SDO GPIO0 GPIO5 DBCK EMI_A21 DWRN TEST1 TEST2 MISO DBIN
TEST4
GPIO4
GPIO7
PGND
DRDN
PVCC
VREF
GND
VDD
XTO
ALE
XTI
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
CGNDA VINL VINR GND VDD VOUTL VOUTR CVDD CGND GPIO3 GPIO6 GPIO2 GND VDD SDA/SS SCL/SCK INTN NRESET DBRQN DBOUT
TQFP80
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PIN FUNCTIONS
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Name EMI_AD5 EMI_AD6 VDD GND EMI_AD7 EMI_A8 EMI_A9 EMI_A10 EMI_A11 EMI_A12 EMI_A13 EMI_A14 EMI_A15 VDD GND EMI_A16 EMI_A17 EMI_A18 EMI_A19 EMI_A20 EMI_A21 DWRN TEST1 TEST2 MISO MOSI VDD GND TEST3 SDI SCK LRCK VDD GND SDO Type I/O I/O I I I/O O O O O O O O O I I O O O O O O O I I I/O I/O I I I I I/O I/O I I O Description EMI Multiplexed Address/Data Line 5. these pin acts as the EMI multiplexed address and data line 5 EMI Multiplexed Address/Data Line 6. these pin acts as the EMI multiplexed address and data line 6 Digital power supply Ground EMI Multiplexed Address/Data Line 7. these pin acts as the EMI multiplexed address and data line 7 EMI Address Line 8. these pin acts as the EMI address line 8. The interface is designed to address up to 4 Mbytes of External Flash, EPROM or SRAM. EMI Address Line 9. these pin acts as the EMI address line 9. EMI Address Line 10. these pin acts as the EMI address line 10. EMI Address Line 11. these pin acts as the EMI address line 11. EMI Address Line 12. these pin acts as the EMI address line 12. EMI Address Line 13. these pin acts as the EMI address line 13. EMI Address Line 14. these pin acts as the EMI address line 14. EMI Address Line 15. these pin acts as the EMI address line 15. Digital power supply Ground EMI Address Line 16. these pin acts as the EMI address line 16. EMI Address Line 17. these pin acts as the EMI address line 17. EMI Address Line 18. these pin acts as the EMI address line 18. EMI Address Line 19. these pin acts as the EMI address line 19. EMI Address Line 20. these pin acts as the EMI address line 20. EMI Address Line 21. these pin acts as the EMI address line 21. EMI Write Enable. This pin serves as the write enable for the EMI Test 1. Used for test: set to LOW for normal operation Test 2. Used for test: set to HIGH for normal operation SPI Master Output Slave Input Serial Data. Serial Data Output for SPI type serial Port when in SPI master Mode and Serial Data Input when in SPI Slave Mode SPI Master Input Slave Output Serial Data. Serial Data Input for SPI type serial Port when in SPI master Mode and Serial Data Output when in SPI Slave Mode Digital Power Supply Ground Test 3. Used for test: set to LOW for normal operation SAI Data Input SAI Bit Clock SAI Left/Right Clock Digital power supply Ground SAI Data Output
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PIN FUNCTIONS (continued)
N. 36 37 38 39 40 41 42 43 44 45 Name GPIO1 GPIO0 GPIO5 DBCK DBIN DBOUT DBRQN NRESET INTN SCL/SCK Type I/O I/O I/O I/O I/O I/O I I I I/O I/O 46 SDA/SS I/O I 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 VDD GND GPIO2 GPIO6 GPIO3 CGND CVDD VOUTR VOUTL VDD GND VINR VINL CGNDA TEST4 CVDDA VREF REFCAP GPIO7 GPIO4 VDD CLKOUT I I I/O I/O I/O I I O O I I I I I O I O O I/O I/O I O General Purpose I/O General Purpose I/O General Purpose I/O Debug port Bit Clock/Chip Status 1. The serial clock for the Debug Port is provided. May also be used as GPIO9. Debug port Serial Input/Chip Status 0. The serial data input for the Debug Port is provided. May also be used as GPIO11. Debug Port Serial Output. This pin is the serial Data output for the Debug port. May also be used as GPIO10. Debug Port Request Input. This pin is used to request Debug Mode operation to Euterpe System Reset. A low level applied to RESET input initializes the IC. External interrupt line. When this line is asserted low the DSP may be interrupted. I2C Serial Clock Line. Clock line for I2C bus. Schmitt trigger input. SPI Bit Clock. If SPI interface is enabled, it behaves as SPI bit clock. I2C Serial Data Line. Data line for I2C bus. Schmitt trigger input. SPI Slave Select. If SPI interface is enabled, it behaves as Slave select line for SPI bus. Digital Power Supply Ground General Purpose I/O General Purpose I/O General Purpose I/O Ground for the internal CODEC cell Power Supply for the internal CODEC cell Single-ended right channel analogue output from DAC Single-ended left channel analogue output from DAC Digital power supply Ground Single-ended right channel analogue input to ADC Single-ended left channel analogue input to ADC Ground for the internal CODEC cell Connect a 22K pull-down resistor Power Supply for the internal CODEC cell Voltage Reference from the CODEC cell Voltage Reference Capacitor Bypass General Purpose I/O General Purpose I/O Digital power supply Clock Output. Output Clock divided down from PLL Description
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PIN FUNCTIONS (continued)
N. 69 70 71 72 73 74 75 76 77 78 79 80 Name XTI PGND PVCC XTO ALE GND DRDN EMI_AD0 EMI_AD1 EMI_AD2 EMI_AD3 EMI_AD4 Type I O I O O I O I/O I/O I/O I/O I/O Description Crystal Oscillator Input. Crystal Oscillator Input drive PLL Ground Input. Ground connection for Oscillator circuit PLL Power Supply Positive. Supply for PLL Clock Oscillator Crystal Oscillator Output. Crystal Oscillator Output drive EMI Address Latch Enable. This pin acts as the EMI Address Latch Enable for the External Memory Interface Ground EMI Read Enable. This pin serves as the read enable for the EMI EMI Multiplexed Address/Data Line 0. these pin acts as the EMI multiplexed address and data line 0 EMI Multiplexed Address/Data Line 1. these pin acts as the EMI multiplexed address and data line 1 EMI Multiplexed Address/Data Line 2. these pin acts as the EMI multiplexed address and data line 2 EMI Multiplexed Address/Data Line 3. these pin acts as the EMI multiplexed address and data line 3 EMI Multiplexed Address/Data Line 4. these pin acts as the EMI multiplexed address and data line 4
RECOMMENDED DC OPERATING CONDITIONS
Symbol VDD TJ Parameter Power Supply Volrage Range Operating Junction Temp. Test Condition Min. 3 -40 Typ. 3.3 Max. 3.6 125 Unit V C
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24 BIT DSP CORE The DSP Core is a general purpose 24-bit DSP. The main feature of the DSP Core are listed below: 50Mhz Operating Frequency (50 MIPS) Single cycle multiply and accumulate 2x56-bit Accumulators Double precision multiply Convergent rounding Scaling and saturation arithmetic 48-bit or 2x24-bit parallel moves 64 interrupt vector locations Fast or long interrupts possible Programmable interrupt priorities and masking 8 each Address Registers, Address Offset Registers and Address Modulo Registers Linear, Reverse Carry, Multiple Buffer Modulo, Multiple Wrap-around Modulo address arithmetic Post-increment or decrement by 1 or by offset, Index by offset, predecrement address Repeat instruction and zero overhead DO loops Hardware stackcapable of nesting 7 DO loops or 15 interrupts/subroutines Bit manipulation instructions possible on all registers and memory locations. Also Jump on bit test. Data Arithmetic Logic Unit (DALU) Address Generation Unit (AGU) Program Control Unit (PCU) Three Data Buses Three Address Buses Internal Data Bus Switch bit Manipulation Unit Debug Logic Memories 16384x24-bit Program ROM used for storing the program code. 16384x24-bit Data RAM used for storing Data. - Master and Slave Operating Modes - Reference clock for transmission supplied - Transmit and Receive Interrupt Logic modified to trigger on Left/Right data pairs - Receive and Transmit Data Registers have two locations to hold left and right data I2C interface/SPI The inter integrated-circuit bus is a simple bidirectional two-wire bus used for efficient inter IC control. All I2C bus compatible devices incorporate an on-chip interface which allows them communicate directly with each via the I2C bus. Every component hoocked up to the I2C bus has it's own unique address whether it is a CPU, memory or some other complex function chip. Each of these chips can act as a receiver and/or transmitter depending on it's functionality. The Serial Peripheral Interface (SPI) can be enabled instead of the I2C interface. During an SPI transfer, data is trasmitted and received simulaneously. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slve SPI device. When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit character is simultaneously shifted in a second data pin. The central element in the SPI system is the shift register and the read data buffer. The system is single buffered in the trasmit direction and double buffered in the receive direction. EMI The External Memory Interface is viewed as a memory mapped peripheral. Data transfers are performed by moving data into/from data registers and the control is exercised by polling status flags in the control/status register or by servicing interrupts. An external memory write is executed by writing data into the Data Write register. An external memory read operation is executed by either writing to the Offset register or reading the Data read register, depending on the configuration. The main features of the EMI are listed below: - Data bus width fixed at 4 bits for DRAM and 8 bits for SRAM - 22 bit address bus multiplexed with an 8 bit data bus - Three choices of data word lenghths, 8, 16 or 24 bits in SRAM mode - Two choices of data word lenght, 16 or 24 bits in DRAM mode - Thirteen address lines 226= 256Mbits
DSP peripherals Serial Audio Interface (SAI) The SAI is used to deliver digital audio to the DSP from an external source and to deliver digital audio from the DSP to an external DAC. It allows using an external CODEC. The main features of this block are listed below: - One Data Transmission Line - One Data Reception Line
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addressable DRAM - Refresh rate for DRAM can be chosen among sixteen divide factors - SRAM or DRAM relative addressing modes - 222=4MBytes addressable SRAM - Four SRAM Timing choices - Two Read Offset Register PLL The Euterpe clock system generates the following clocks: - DCLK the DSP core clock - MCLK CODEC master clock - LRCLK left/right clock for the SAI and the CODEC - SCLK shift serial clock for the SAI and the CODEC The output of the PLL operates from 70 to 140 MHz. The DSP core can operate with a clock up to 50 MHz. DEVICE versions
Part No. TDA7550R TDA7550 Internal Program Memory RAM ROM Function One of the below Speech Recognition Serial I/F Master or Slave I2C Slave I2C External Memory FLASH or RAM FLASH Audio Input YES (by appl.) YES, 1 (voice in) Audio Output YES (by appl.) YES (prompts) Software Custom Specs. ASR-311 Engine by Lernout & Hauspie SV208 Engine by Lernout & Hauspie TTS3000 Engine by Lernout & Hauspie Engine by NCTI
From the VCO output the audio clock are derived. CODEC The main features of the CODEC are listed below: - one 16-bit Delta Sigma Stereo ADC - 80 dB Dynamic Range - Oversampling Ratio: 128 - one 16-bit Delta Sigma Stereo DAC - 80 dB Dynamic Range - Interpolating Ratio: 128 - Sampling rates of 4kHz to 48kHz - Signal Noise Ratio: 80 dB Typ. The analog interface is in the form of differential signals for each channel. The interface on the digital side has the form of an SAI interface and can interface directly to an SAI channel and then to the DSP core.
TDA7551
Speaker Verification
Slave I2C
Optional FLASH
YES, 1 (voice in)
YES (prompts)
TDA7552
Text-ToSpeech
Slave I2C
-
NO
YES (voice out)
TDA7553
SF/FDE
Master I2C or SPI
(RAM)
YES, 1 (voice in)
YES (filtered)
Note: TDA7550 requires word databases on FLASH (cfr. Document words)
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TDA7550 ASR311 Automatic Speech Recognition solution The TDA-7550 is a single-chip solution for isolated word speech recognition, featuring the Lernout & Hauspie ASR311 Automatic Speech Recognition engine.
Word base recognition Isolated word recognition Quasi-connected digit recognition Noise-robust recognition Speaker-independent recognition Speaker-dependent recognition Training phase Prompts Control through I2C The words database is created from an extensive set of recordings, with an equal distribution of speakers; the recordings are partially taken in automotive conditions at low, medium and high speed. Minimum pause between two numbers 150ms. The recognition is still very robust even in high noisy environment (as automotive or industrial environments) Recognition is affected by selected language, no training is required User words can be stored and mixed with speaker-independent words User words can be trained by repeating three times the selected word. Recognition is guaranteed when the same speaker is talking. Voice prompts can be stored on FLASH for creating a voice-based user interface Management of the recognition engine, user words and voice prompts is accomplished through an I2C protocol: the TDA7550 appears as a slave I2C device. Vocabularies in the following languages are available: US English, French, German, Italian, Spanish, Japanese. All the vocabularies have a common subset of about 150 words. Other words and languages are available on request. Speaker Independent vocabulary (4 KB/word) User Words (4 KB/word) Voice prompts (11 KB/sec) 11.025 kHz > 95% 30 450 4 KB (speaker-independent) 4 KB (speaker-dependent) 11 KB/s
Many languages available
The external FLASH is used to store:
Sample rate: Recognition rate: Maximum number of active words: Maximum number of words: Word memory requirements: Prompt memory requirements:
Figure 1.
audio amp mic preamp spkr
ADC
DAC
TDA7550
C
slave I C
service request
2
EMI
FLASH bank
Up to 4 MB
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TDA7551 SV208 Speaker Verification solution The TDA7551 is a single-chip solution for speaker verification, featuring the Lernout & Hauspie SV208 verification engine. Pass-phrases can be stored by performing an enrollment (the pass-phrase must be repeated three times), then the incoming prompt can be compared with the pre-stored pass-phrase to verify the speaker identity.
Known password speaker recognition Enrollment phase Noise-robust recognition of isolated words The speaker associates his identity to an utterance, which must last from 1 to 2 seconds, and reapeat it three times; the algorithm performs an analysis and accepts or rejects the enrollment phase. The claimed identity of the speaker is compared with the result of the verification phase, in which the input prompt is compared with the selected pass-phrase. Management of the verification engine is accomplished through an I 2C protocol: the TDA7551 appears as a slave I2C device. 8 kHz > 94%
Verification phase
Control through I2C
Sample rate: Equal error rate:
Figure 2.
mic preamp
audio amp (optional)
to external world
ADC DAC
spkr
Controller
slave I2C
service request
TDA7551
EMI
FLASH b an k
Up to 4 MB
Pass-phrases can reside here
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TDA7552 TTS3000 Text-To-Speech solution The TDA7551 is part of a two-chip solution for Text-To-Speech, featuring the Lernout & Hauspie TTS3000 engine. Two devices are needed: * A 16-bit microcontroller (ST10) for string analysis and conversion * The TDA7552 DSP for voice synthesis. An external application sends ASCII strings to the microcontroller, which perform an analysis of the entire sentence; language-dependent data is needed on the FLASH accessed by the ST10. As a result of the analysis, a data stream is sent through I2C to the TDS7552 DSP. No external memory is required by the DSP. The software running on the TDA7552 DSP is independent from languages.
Control through I2C Many languages available Management of the DSP is accomplished through an I2C protocol: the TDA7552 appears as a slave i2c device. The following languages are available: US English, French, German, Italian, Spanish, Japanese. Other languages available on request. 11.025 kHz
Sample rate:
Figure 3.
audio amp
ASCII string
ST10
microcontroller
IC
2
TDA7552
language-independent code languagedependent code
FLASH bank
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DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.22 0.09
mm TYP. MAX. 1.60 0.15 1.40 0.32 1.45 0.38 0.20 16.00 14.00 12.35 0.65 16.00 14.00 12.35 0.60 1.00 0.75 0.018 0.002 0.053 0.009 0.003 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.013 0.057 0.015 0.008 0.630 0.551 0.295 0.0256 0.630 0.551 0.486 0.024 0.0393 3.5(min.), 7(max.) 0.030
OUTLINE AND MECHANICAL DATA
TQFP80 (14x14x1.40mm)
D D1 D3
A A2
A1
60 61 41 40
0.10mm .004 Seating Plane
e
E3 B
E1
E
PIN 1 IDENTIFICATION
Gage plane 0.25mm
80 1 20
21
K
TQFP80L
C L L1
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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